1. Field of the Invention
The present invention relates to a chip package. More particularly, the present invention relates to a bump-less build-up layer (BBUL) type of chip package.
2. Description of the Related Art
With the rapid development of new electronic technologies, the electronic devices have developed to have higher processing speed, multi-function, high integration, miniaturized size and low cost. As a result, chip packaging is also developing towards miniaturization and densification. The conventional ball grid array (BGA) packaging technique often utilizes a package substrate to serve as a carrier for an integrated circuit (IC) chip and then applies flip-chip bonding or a wire bonding method to electrically connect the the chip to the top surface of the package substrate. Then, a plurality of solder balls are disposed on a bottom surface of the package substrate to form an area array. Thus, the chip can electrically connect with an electronic component in the next level, such as a printed circuit board, through an electrical circuit inside the package substrate and the solder balls at the bottom surface of the package substrate.
However, since the conventional BGA packaging technique requires a high layout density package substrate, together with a flip-chip bonding or wire bonding electrical connection, signal transmission pathway becomes too long. In solution, a new type of chip packaging technique, called the bump-less build-up layer (BBUL) method, has been developed. In the BBUL method, flip-chip bonding or wire bonding is omitted. Instead, a multi-layered interconnection structure is directly fabricated on the chip and then a plurality of electrical contacts, such as solder balls or pins, are disposed on the multi-layered interconnection structure to form an area array for electrically connecting with an electrical component in the next level.
FIG. 1 is a schematic cross-sectional view of a conventional bump-less build-up layer (BBUL) chip package. As shown in FIG. 1, the bump-less build-up layer chip package 100 mainly comprises a stiffener 110, a chip 120, an interconnection structure 130, an encapsulating layer 140 and a plurality of solder balls 150. The stiffener 110 has an opening 110a and the chip 120 is disposed inside the opening 110a. The encapsulating layer 140 is disposed between the chip 120 and the inner surfaces of the opening 110a. The chip 120 has a plurality of bonding pads 122 on its active surface. The interconnection structure 130 is disposed on the active surface of the chip 120 and is electrically connected to the bonding pads 122.
The interconnection structure 130 further comprises a plurality of dielectric layers 132, a plurality of circuit layers 134 and a plurality of conductive vias 134a. The circuit layers 134 are sequentially stacked over the chip 120 and the stiffener 110, and one of the circuit layers 134 closest to the chip 120 is electrically connected to the pads 122 on the chip 120 through the conductive vias 134a. In addition, each dielectric layer 132 is disposed between two neighboring circuit layers 134 and each conductive via 134a passes through one of the dielectric layers 132 for electrically connecting at least two circuit layers 134. Furthermore, the conventional BBUL package chip 100 includes a plurality of bonding pads 160 and a solder mask layer 170. The bonding pads 160 are disposed on the interconnection structure 130, and the solder mask layer 170 is disposed on the interconnection structure 130 to expose the bonding pads 160. The solder balls 150 are disposed over the bonding pads 160, respectively.
Although the conventional bump-less build-up layer chip package 100 has good reliability and high electrical performance, the problem of cross talk at high frequency transmission is increasingly serious due to increased circuit layout density and reduced line pitch. In other words, the quality of the BBUL package chip 100 will deteriorate as the circuit layout density is increased and the line pitch is reduced.